ASIC Physical Design Engineer - Data Center GPU Job Listing at AMD in Santa Clara, CA (Job ID 56522-en-us)

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_

THE ROLE:

AMD is looking for an ASIC Physical Design Engineer to be part of the next generation Datacenter GPU SOC Design Team in Santa Clara.

THE PERSON:

You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc.  You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you.

 
KEY RESPONSIBILITIES:

• Lead engineer driving PPA improvements in both pre-silicon and post-silicon design phase.
• Drive cross-functional teams (technology, CAD tools, platform characterization, binning  practices and design methodology).
• Optimize margining practices across boundaries to deliver best in class performance/watt.
• Improve low voltage margining methodology and design practices to improve Vmin and performance/watt for low power GFXIP.
• Drive design practices to improve boost frequency for GFXIP.
• Drive silicon correlation and deliver systematic improvements to improve silicon to STA on high performance Graphics IP.

PREFERRED EXPERIENCE: 

• Prior experience in ASIC Physical Design from RTL to GDSII.
• Strong RTL analysis skills including Verilog, Timing Analysis, and library understanding.
• Strong knowledge in design margining methodology, low voltage design, silicon – STA correlation.
• Hands on experience in taping out 3nm, 5nm, 7nm and/or 16nm SOC.
• Working experience on CAD tools from Synopsys, Cadence and Mentor Graphics.
• Strong communication, time management, and presentation skills.
• Excellent analytical, problem solving, and attention to detail skills.
• Must be a self-starter, and be able to independently and efficiently drive tasks to completion.
• Provide mentorship and guidance to junior and senior engineers, and be an effective team player.

ACADEMIC CREDENTIALS: 

• Bachelor's or Master's degree in Computer Engineering, Computer Science or Electrical Engineering is desired.

If you have the above required skills and are looking for a career opportunity to step up, this is the position for you. Join us and lead the world together.

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At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD's Employee Stock Purchase Plan. You'll also be eligible for competitive benefits described in more detail here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.