Sr. Silicon Design Engineer ( Senior DFT Engineer ) Job Listing at AMD in Hyderabad, TS (Job ID 38343-en-us)

Description

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SENIOR SILICON DESIGN ENGINEER 

THE ROLE: 

The product verification team is seeking a Senior Silicon Design Engineer to have an exciting career on Scan, MBIST, iJTAG test development of latest 7nm MPSoC (Multi Processor System on Chip) products and beyond. The IPs range from ARM based Processor to critical IPs which provide automotive, data centre, machine learning and high-speed communication solutions. You will work closely with designers to make sure DFT structures are correctly inserted, with test engineers to make sure ATE test programs can be generated from the DFT (ATPG, MBIST) tools, with product engineers to make sure scan/mbist production test can run seamlessly and stable, and with yield engineers to debug and root-cause failures/defects. You will also be creating RTL design utilizing FPGA fabric resources to build communication logic for stimulus and response delivery between device and ATE.

THE PERSON: 

Good communication skills, works well in a group environment that spans across continents. Open for challenges and adaptable to the work environment.

KEY RESPONSIBILITIES: 

• Work closely with design team and make sure DFT structures are correctly inserted.
• Responsible for developing, implementing and verifying DFT schemes on hard-IPs in FPGAs.
• Responsible for developing and implementing techniques to test digital logic, using Scan Compression, Stuck-at, Transition and Path-Delay fault models
• Responsible for developing mbist patterns
• Responsible for debugging of pattern issues on bench/ATE to root cause the problem
• Collaborate closely with the New Product Introduction and Test/Product teams to ensure timely delivery of robust test patterns
• Assist in Diagnosis and Yield enhancement through product lifecycle
• Responsible to develop Firmware driven cost-effective test strategies/methodologies with built-in diagnosis capability to enable efficient debugging and fault isolation on bench/ATE

PREFERRED EXPERIENCE: 

• Experience in creating and implementing complex chip-level DFT architecture.
• Experience in DFT implementation including Scan and Scan Compression at IP and SoC level.
• Experience with DFT tools, ATPG (Stuck-At, At-Speed, Path-Delay) and scan compression.
• Proficient in logic design using Verilog and experience in synthesis and STA
• Experience in developing test benches and simulation in RTL/GATE/SDF environments
• Knowledge of MBIST is a plus.
• Knowledge of FPGA synthesis and design flow is a plus
• Experience with post-silicon debug and bench setup is a plus
• Comfortable in Linux environment and writing/using scripting languages such as Perl, Tcl, etc

ACADEMIC CREDENTIALS: 

• BS or MS in Electrical/Electronic/Computer Engineering with 5+Yrs of exp .
• Prior experience as DFT engineer.
• Any Tessent Scan/ATPG/MBIST certifications is a plus.

Location: Hyderabad

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Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.