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Company: AMD
Location: Bengaluru, KA, India
Career Level: Mid-Senior Level
Industries: Technology, Software, IT, Electronics

Description



WHAT YOU DO AT AMD CHANGES EVERYTHING 

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.  Together, we advance your career.  



SMTS Silicon Design Engineer

 

THE ROLE:

The Core design and verification team is responsible for development of ‘High performance and Ultralow power x86 microprocessor core'. The role provides a unique opportunity to work at the micro-architectural level of the next-gen Core, with exposure to designs that defines the next wave of client (laptops/ultra-books/think-clients) and custom designs. The multi-billion gate complexity and high-frequency (GHz) design development gives the learning experience of the latest and greatest design and verification methodologies, using cutting edge advanced technology nodes.

 

THE PERSON:

Candidates should have solid track record of working on complex SoC designs with hands on experience on Post silicon Vaidation, System level Debug, Driving cross functional task forces. solid understanding of X86 architecture, power management concepts, Design verification methodologies. 

 

KEY RESPONSIBLITIES:

  • Own Post silicon validation of core power management functionality
  • Architecting test plans, test content generation and silicon validation execution
  • co-ordniate with cross functional teams for validation planning for cross team functionality and drive the validation closure
  • Drive Silicon debugs across different functional teams and work with RTL/Design verification teams to root cause, escape analysis, help improve pre-si verification strength
  • lead Program/project execution for Silicon/Pre-Si verification activities for Power managment function
  •  

PREFERRED EXPERIENCE:

  • 15yrs of experience in complex SoC Pre-Si/Post Silicon verification
  • Strong understanding the design and verification life cycle.
  • Strong system debug capabilities and hands on experience of Debug tools and methodologies like JTAG, Scan dump
  • Experience with x86, ARM or any other industry standard microprocessor architecture and ACPI standards.
  • Experience in clocking, reset, power-up sequences and power management verification.
  • Understanding of low power design verification techniques is a plus.
  • exposure to Emulation, Power aware verification methodologies is a plus

ACADEMIC CREDENTIALS:

  • Bachelor or Master's Degree in Electronics/Computer Engineering


Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

 

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD's “Responsible AI Policy” is available here.

 

This posting is for an existing vacancy.


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