Programmable Clock - Adaptive Computing Group , Circuit Design lead Job Listing at AMD in Hyderabad, TS (Job ID 57737-en-us)

Description

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Programmable Clock - Adaptive Computing Group , Circuit Design lead

THE ROLE: 

As the part of the Programmable Clock & Methodologies team in India for AMD's Adaptive-Embedded Computing products, you will be responsible for design and development of clocking solutions that meet the high standards of AMD's AECG products. This will involve working a team of highly skilled engineers in India, as well as with the global Clock team of experts at the San Jose office.

An integral part of AMD's programmable logic group, the global Clock team is tasked with implementing the programmable clock for AMD's growing range of Adaptive-Embedded Computing products. Every new Adaptive SOC brings a new set of programable Clock challenges with their latest system, functional architectures and their adoption of new semiconductor and packaging technologies. The Global Clock team works closely with functional architecture, other Programable Logic groups, integration and SW teams to craft and implement new clock solutions, including new architectures, Clock Ips, PLL integrations post-Silicon ‘Validation & Characterization' and development of new tools, flows & Methodology.

This position invites candidates to join a clock team of experts, inventing and implementing original solutions, addressing challenging clock problems in some of the industry's largest and most complex SOCs.

THE PERSON:

You will lead by bringing people together and drive towards consensus, decisions, and results. Working independently, you will convert high level concepts down to tangible specifications that can be implemented efficiently. You should enjoy collaborating with engineers with their diverse skillsets and bring their expertise to bear on solving challenging Programable Clock problems.

 KEY RESPONSIBILITIES:

• Design and development of new Clock architectures and Circuits solution, Determine creative design approaches and parameters.
• Mixed-mode simulation (analog/digital co-simulation) at SoC level, including chiplet base SoC.
• Lead PLL integration and interface design for complex SoC requirement for high performance and power efficient Global Clock.
• Test, debug, yield, post-Silicon Validation & Characterization of the Programmable Clock.
• Programable global Clock distribution methodologies optimizing Clock - Skew, Jitter, DCD, Signal integrity and power integrity issues.
• Contribute to architecture specification and circuit design for advanced energy efficient Programable Clock, deskew Circuit etc.
• Supervise layout design with floorplan and signal flow guidance. Post-layout simulation for reliability checks such as Aging/self heating/Monte Carlo/electromigration etc.
• Work and collaborate with domain teams (e.g. Layout, Logical Design, Physical Design, Integration and SW)
• Implement IP in FPGA environment using Vivado or similar tools/flows.

PREFERRED EXPERIENCE:

• You should have a deep understanding of Clocking methodologies and experience in leading teams to deliver complex projects. Working knowledge of Programable clocking is a plus.
•  Experience in Mixed-mode simulation (analog/digital co-simulation), Debugging simulation failures in both analog and digital domains
• PLL integration and interface design for complex SoC.
• Experience in Clock Calibrated De-skew design is a plus.
• Understanding of Analog/Digital Design, microelectronics, electrical systems and Software development
• Strong Clock circuit fundamentals (Clock switching and gating, synchronization, Divider, Clock skew balancing, Jitter, Fmax, DCD and CDC analysis).
• Working experience of Package level Clock SIPI including transmission line and EM wave theory is a plus
• Familiarity with test, debug, yield, post-Silicon Validation & Characterization is a plus.
• You should be an expert in the development of clocking solutions and have the ability to work effectively with global teams (USA & India) to ensure that on time product delivery with high quality is met.
• Circuit Design Tools: Cadence (Virtuoso - Schematics and Layout), ADE-XL, Spectre.
• Prior work experience in FPGA design using VIVADO tool and silicon testing is a plus.

ACADEMIC CREDENTIALS: 

• Bachelor or master degree in computer engineering/Electronics or Electrical Engineering with 12-15+ years of exp 

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Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.