ASIC Implementation Engineer Job Listing at AMD in Santa Clara, CA (Job ID 69174-en-us)

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_

THE ROLE: 

Our NTSG – Network Technology Solutions Group team working with our AMD Pensando DPU product's is a leading provider of innovative solutions in the field of data center infrastructure, AI NIC (GPU-to-GPU communication) and networking technologies. We are looking for a dynamic, energetic candidate to join our team in the AMD Pensando DPU Group.

We are seeking a highly motivated and experienced ASIC Implementation Engineer to join our dynamic team. The ideal candidate will be responsible for leading the implementation of complex ASIC designs, from synthesis to tape-out, while working closely with architects, designers, and physical design teams.

THE PERSON:  

You have a passion for modern technology, complex processor architecture, digital design. You are a team player who has excellent communication skills, proactive approach and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. 

KEY RESPONSABILITIES:

• Run Logic/Physical synthesis using advanced techniques to generate netlists with optimized power, performance, and area.
• Perform logic equivalency checks for blocks/chip and analyze/debug the results.
• Conduct Flat and Hierarchical clock domain crossing and collaborate with designers to analyze complex clock domain crossings.
• Execute Flat and Hierarchical reset domain crossing checks and understand reset architecture by working closely with designers.
• Perform RTL Lint and work with designers to create waivers.
• Create timing constraints for synthesis.
• Develop automation scripts and methodologies for all Front-end tools including LINT, CDC, RDC, SYN, LEC.

PREFERRED QUALIFICATIONS:

• Strong experience in Synthesis.
• Experience with LINT, Clock domain crossing, and reset domain crossing signoff.
• Proficiency in Logic equivalency checks.
• Knowledge of front-end ASIC flows.
• Experience in communicating across functional internal teams and vendors.
• Scripting and programming experience using Perl, TCL, Python, Cshell, and Make.
• Experience with SOC design integration and Front-end implementation.
• Knowledge of Timing/physical libraries and memories.
• Familiarity with Design Compiler, Fusion Compiler, Spyglass, Zero-in, Primetime, Formality, and Conformal LEC.

ACADEMIC CREDENTIALS:

BSEE or equivalent. MSEE preferred

LOCATION:

Santa Clara, CA

#LI-BW1

#LI-hybrid

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.