SR ASIC SoC Design Engineer Job Listing at AMD in Santa Clara, CA (Job ID 80779-en-us)

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING 

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.  Together, we advance your career.  

THE TEAM – NETWORKING TECHNOLOGY SOLUTIONS GROUP (NTSG) 

AMD's Networking Technology Solutions Group (NTSG) is a leading provider of data center and AI networking technologies. NTSG develops high performance, scalable networking silicon and platforms that power modern cloud, enterprise, and AI infrastructure. Our solutions include advanced ASICs and SoCs that enable high bandwidth, low latency data movement and acceleration for next generation AI and distributed computing workloads. 

THE ROLE:

We are seeking a Senior Member of Technical Staff (SMTS) ASIC SoC Design Engineer to join our NTSG silicon development team. In this role, you will be a senior technical contributor responsible for designing and integrating complex SoC subsystems for AI networking ASICs, including both monolithic and chiplet based SoC architectures. 

You will work across the full development lifecycle—from architecture and microarchitecture definition through RTL implementation, integration, and silicon bring up—collaborating closely with architecture, verification, physical design, firmware, and software teams to deliver robust, scalable SoC solutions for next generation AI networking products. 
You will operate within a broader SoC architecture and execution framework while owning critical subsystems and integration paths. 

THE PERSON:

The ideal candidate is a seasoned SoC / ASIC engineer with strong system level thinking and a track record of delivering complex silicon in production. You combine deep technical expertise with a growth mindset, curiosity about emerging AI technologies, and a passion for improving engineering productivity. 

You are comfortable operating at the SMTS level—owning ambiguous problems, influencing technical direction, and collaborating across organizational boundaries to deliver high impact results.

KEY RESPONSIBILITIES:

• Lead SoC level design and integration of embedded subsystems including CPUs, NoCs, and peripheral IPs for advanced AI networking ASICs 

• Drive integration using SoC IP generation and configuration tools, including NoC, AMBA protocol converters, and CSR generation frameworks 

• Design and integrate PCIe subsystems and DMA engines, including configuration, data movement, and performance optimization 

• Own and review reset architecture, boot flows, and security initialization sequences at the SoC level, collaborating with firmware and security teams 

• Support chiplet based SoC integration, including die-to-die connectivity and system level considerations 

• Support system level validation and bring-up of chiplet-based SoCs across multiple dies 

• Drive high quality RTL implementation, reviews, and integration across multiple IP blocks and subsystems 

• Support full ASIC development lifecycle activities including lint/CDC, synthesis, integration debug, emulation, and post silicon bring-up 

• Debug complex SoC integration issues in simulation, emulation, and silicon 

• Continuously explore and adopt AI-assisted design and productivity tools to improve development efficiency and design quality 

 REQUIRED QUALIFICATIONS:

• Significant hands-on experience in ASIC / SoC development from architecture through silicon bring-up 

• Proven experience with embedded SoC architectures including CPUs and NoCs using AMBA protocols (AXI/AHB/APB) 

• Strong experience with PCIe and DMA architectures 

• Hands-on experience using and integrating SoC IP generation and configuration tools for NoC, AMBA protocol conversion, and CSR generation 

• Proficiency in RTL design using SystemVerilog / Verilog 

• Demonstrated experience delivering production ASIC or SoC silicon 

• Ability to collaborate effectively across hardware, firmware, and software teams 

PREFERRED QUALIFICATIONS:

• Experience with chiplet-based SoC architectures and die-to-die (C2C) connectivity standards such as UCIe 

• Background in AI, networking, or data center class ASICs 

• Exposure to secure boot, hardware root of trust, or security IP integration 

• Experience with emulation, FPGA prototyping, or post silicon debug 

• Interest in applying AI-based tools or methodologies to improve design, integration, or debug productivity 

ACADEMIC CREDENTIALS:

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field 

LOCATION:

Santa Clara, CA

#LI-BW1

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This role is not eligible for visa sponsorship.

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD's “Responsible AI Policy” is available here.

This posting is for an existing vacancy.