Power Optimization & Analysis Engineer Job Listing at AMD in Santa Clara, CA (Job ID 69424-en-us)

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

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THE ROLE:

We are seeking a highly motivated, innovative, and dedicated engineer to join the Power Competitive Group; we are a group that is driving advanced power attainment, power optimization and power management techniques for AMD IPs & Products. We rely on strong analytical skills and close collaboration to deliver the best overall solution. In this highly visible role, you will be at the center of power competitive initiative, with a critical impact on getting high performance products to millions of customers quickly.

THE PERSON:

We are seeking IP power Management engineer who has expertise in power management techniques for di/dt, EDC, and TDC. This role focusses on ensuring power efficient IP/product development across the entire portfolio of AMD IPs. This work is crucial for maximizing performance while maintaining electrical stability and thermal limits, especially in high-demand environments like data centers and gaming systems. 

KEY RESPONSIBILITIES:  

• Defining and managing power limits: These engineers are responsible for defining and managing power limits like EDC (maximum momentary burst/boost current) and TDC (maximum sustained current allowable by precision boost). 
• Simulation and analysis: Engineers conduct simulations and analyze results to ensure the design remains within these current limits and thermal thresholds under various operating conditions.
• Support post-silicon debug for power and thermal issues, potentially involving EDC and TDC limit adjustments to resolve problems or improve system stability
• Designing and verifying power management architectures: This includes developing and evaluating power delivery systems and ensuring their stability and performance.
• Implementing and optimizing power management features: Focusing on techniques like Dynamic Voltage and Frequency Scaling (DVFS), clock gating, and power gating to reduce power consumption and heat generation.
• Analyzing and managing power constraints: Utilizing tools and techniques to understand and optimize the use of power limits like TDP (Thermal Design Power), TGP (Total Graphics Power), TBP (Total Board Power), and the transient current limits like EDC (Electrical Design Current) and TDC (Thermal Design Current).
• Debugging and solving power-related issues: Collaborating with various teams to troubleshoot and resolve issues related to power attainment, power delivery, thermal throttling, and overall system stability.
• Working with cross-functional teams: Collaborating with architects, designers, software/firmware engineers, and other teams to drive successful power methodologies

PREFERRED EXPERIENCE:  

• Expertise in designing and implementing efficient power delivery networks that can handle current demands and voltage fluctuations.
• Knowledge of power integrity concepts and experience with electromigration analysis to ensure long-term reliability of the power delivery system.
• Debugging and verification: Experience in developing and executing test plans, creating and analyzing coverage, and developing checkers and transactors to verify the functionality of power management and clock control logic.
• Expertise in power modeling and analysis tools: Proficiency in simulating and analyzing power consumption and performance characteristics.
• Handson experience with lab equipment: Familiarity with oscilloscopes, probes, and data acquisition equipment for characterization and validation.
• Strong programming and scripting skills: Proficiency in languages like C/C++, Perl, or Python.
• Familiarity with ASIC/SoC design cycles and methodologies: Understanding the process from RTL to post-silicon validation.
• Excellent problem-solving and debugging skills: Ability to identify and resolve complex power-related issues effectively.
• Strong communication and collaboration skills: Ability to work effectively within cross-functional teams and communicate technical information clearly.
• Looking for IP power Management engineers with good knowledge power attainment and power management techniques like di/dt, EDC, and TDC. This is for ensuring optimal performance and reliability of modern GPUs by expertly balancing power consumption, thermal constraints, and transient electrical behavior. 

ACADEMIC CREDENTIALS:  

• Bachelors or Masters in Electrical Engineering or Computer Engineering

LOCATION: Santa Clara, Austin, Orlando, Boston, Folsom

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Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.