MTS Silicon Design Engineer Job Listing at AMD in Shanghai, Shanghai (Job ID 81226-en-us)

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING 

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.  Together, we advance your career.  

THE ROLE: 

AMD IP FEINT team delivers industry leading high-performance interconnects IP for all AMD products including CPU, APU, dGPU, and Game consoles. You'll be working with the global IP/SOC/PD/CAD team to deliver high quality netlists and constraints, support PD team to close P&R timing of tiles, and handles IP design quality check. 

THE PERSON: 

• Strong analytical/problem solving skills and pronounced attention to details. 

• Must be a self starter, and able to independently drive tasks to completion. 

• Strong interpersonal and communication skills. 

• Strong responsibilities and team spirit. 

KEY RESPONSIBILITIES: 

• Responsible for industry leading IP Synthesis/Formal/STA. 

• Responsible for industry leading IP LINT/CDC/VSI. 

• Responsible for industry leading IP regularly regression. 

• Responsible for function ECO implementation and LEC/DRC check. 

• Work with global IP teams to guarantee IP delivery quality. 

• Work with multiple global SOC teams to implement Tile. 

• Work with multiple global SOC teams to accomplish successful tapeout for AMD Sever/Client/dGPU/S3/AECG products. 

• Work with front-end integration team and physical design team on timing closure. 

• Co-ordinating design and implementation activities. 

PREFERRED EXPERIENCE: 

• Minimum 3 years of experience with Verilog a MUST. 

• Familiar with front-end design flow. 

• Experience on synthesis, timing analysis and formal verification. 

• Excellent knowledge of verilog and a scripting language; experience with Perl and TCL is a plus. 

• Low power experience is a plus. 

ACADEMIC CREDENTIALS: 

• Bachelor, Master's degree in Electrical or Computer engineering. 

LOCATION: 

Shanghai

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Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD's “Responsible AI Policy” is available here.

This posting is for an existing vacancy.