Memory Subsystem Design and Integration Engineer Job Listing at AMD in Markham, ON (Job ID 76657-en-us)

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING 

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.  Together, we advance your career.  

THE ROLE

The Memory Subsystem team at AMD is hiring an RTL and Integration Engineer to contribute to the definition, design, development, and integration of high-speed LPDDR/DDR memory subsystem solutions and associated IP.

This role spans IP-level RTL development through full subsystem integration and includes close collaboration with architecture, verification, firmware, BIOS, and physical design teams across multiple geographic locations.

THE PERSON

You are a technically strong RTL and integration engineer with a system-level mindset and a passion for building complex hardware that functions correctly end-to-end. You work effectively across teams and are capable of independently driving assigned tasks to completion.

KEY RESPONSIBILITIES

• Design, develop, and maintain RTL for memory subsystem IP and integration logic using Verilog/System Verilog
• Participate in architecture and micro-architecture definition and translate requirements into RTL
• Integrate IP blocks to build complete DDR/LPDDR memory subsystems
• Collaborate with verification teams on test plans, debug, and pre-silicon issue resolution
• Work with physical design teams on timing targets, floor planning, and CDC strategies
• Analyze and debug complex functional, timing, and integration issues
• Develop and maintain subsystem documentation and timing diagrams
• Support pre-silicon and post-silicon bring-up activities

PREFERRED EXPERIENCE

• Experience with DDR/JEDEC standard IP, DDR PHY, memory controllers, or memory subsystems
• Experience stitching IP blocks to build complete subsystems
• Knowledge of SVA/OVL and synthesizable assertions
• Exposure to VCS and/or Zebu emulation
• Understanding of power management, UPF, and low-power design concepts
• Strong fundamental and foundational knowledge and application of Object-Oriented Programming concepts
• Strong proficiency in Verilog and System Verilog for RTL design
• Experience designing and integrating IP and subsystems in complex SoC environments
• Understanding of clocking, resets, CDC, and synchronization techniques
• Ability to debug RTL and integration issues using simulation tools
• Experience collaborating with verification, firmware, and physical design teams
• Familiarity with Git and/or Perforce

ACADEMIC CREDENTIALS

• Bachelor's or master's degree (or equivalent) in Electrical Engineering, Computer Engineering, Computer Science, or a related field

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Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.