Lead Graphics Memory Power Architect, Performance Optimization Job Listing at AMD in Santa Clara, CA (Job ID 72429-en-us)

THE ROLE: 

As a Lead Graphics Memory Power Architect, Performance Optimization, you will lead architectural power optimization efforts across memory-related components in AMD's next-generation GPU and APU products. You will be part of a cross-functional architecture team focused on delivering industry-leading performance-per-watt (PPA) across compute, gaming, and AI workloads. This role is central to AMD's “shift-left” initiative—embedding power efficiency early in the architecture phase to reduce downstream design costs and improve silicon efficiency.

THE PERSON: 

You have a passion for modern, complex GFX architecture and digital design. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. 

Leadership Skills: 

• Accomplished listener who can analyze, abstract, communicate, and converge on the best ideas.
• Develop strong partnerships with product stakeholders across the organization and development partners outside the organization.
• Excellent verbal communication and written, presentation skills.
• Excellent interpersonal, organizational, analytical, planning, and teamwork skills.
• A drive to continuously learn and expand architectural breadth and depth

KEY RESPONSIBILITIES: 

• Architect and implement power optimization strategies for memory subsystems including cache hierarchies, compression engines, coherency protocols, and interconnects.
• Collaborate with RTL, PD, software, and modeling teams to define and validate architectural features that improve PPA.
• Analyze game traces and real-world workloads to identify power hotspots and propose mitigation strategies.
• Develop and maintain power models for memory subsystems and validate against silicon measurements.
• Lead architectural reviews and provide technical guidance on Di/Dt mitigation, clock gating, power gating, and wake-up latency.
• Contribute to architectural specifications and programming guides, including power chapters.
• Engage with internal stakeholders and external partners to align on power goals and trade-offs.

• Guide HW Design teams in evaluating and improving power efficiency of their implementations

PREFERRED EXPERIENCE:

• Strong understanding of memory architecture: caches (L1/L2), DRAM interfaces, coherency, compression, and selective coherence.
• Experience with power modeling tools and methodologies.
• Familiarity with GPU architecture and shader workloads.
• Ability to analyze RTL and system-level power behavior.
• Proficiency in scripting and modeling languages (Python, C, RTL).
• Excellent communication and collaboration skills across time zones and disciplines.

ACADEMIC CREDENTIALS: 

• An undergraduate degree is required. A Master's or PhD in Computer Engineering or Electrical Engineering is preferred, along with mastery of logic and circuit design principles, and hardware methods relevant to complex systems and platforms.

LOCATION:

• Santa Clara, CA - Austin, TX - Folsom, CA

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Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.