Lead Embedded CPU PPA Architect Job Listing at AMD in Santa Clara, CA (Job ID 88882-en-us)

Description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we're looking for talent who feel the same: people who want to leave the planet better than they found it, those who don't shy away from humanity's challenges but are determined to help solve them.

AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you're designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward.

THE ROLE:

We are seeking a Lead PPA Architect to ensure that CPU Core & Cache complexes used in embedded products meets the product performance requirements while operating within reliability and system platform constraints. This is a technical leadership role ensuring interlock between CPU IP definition from the Cores design team and the Embedded BU's unique per-product usage model and operating conditions, and the package & platform impact to the power delivery network and thermal management.

THE PERSON: 

You will be a proven technical leader with the ability to drive cross-functional alignment and execution across architecture, physical design implementation, FW/BIOS, SIPI, and platform teams, ensuring timely closure and multi-dimensional alignment of reliability, power delivery, thermal management and performance constraints. You will also be highly organized and execution-driven, with demonstrated success owning end-to-end technical workstreams and driving closure of open issues, risks, and dependencies across program milestones.

KEY RESPONSIBILITIES

• Lead power, performance, area (PPA), thermal, and reliability architecture for CPU Core and Cache complexes, ensuring alignment between product usage models, operating conditions, platform constraints, and CPU IP capabilities.
• Drive cross-functional alignment across CPU architecture, physical design, FW/BIOS, SIPI, package, and platform teams to establish power delivery, thermal management, and performance targets that enable efficient and reliable product operation.
• Translate product workloads, reliability requirements, and system constraints into actionable power, performance, and thermal objectives, influencing SoC, package, and platform architectural decisions while driving alignment between Embedded product roadmaps and available CPU IP solutions.
• Partner closely with power and performance modeling, power delivery, thermal, and reliability teams to define assumptions, targets, and operating conditions, using modeling insights to drive architectural tradeoffs, bounding box readiness, and program execution.
• Own performance and power readiness for major program milestones, driving technical reviews, risk management, issue resolution, and executive-level decision making across the product development lifecycle.

PREFERRED EXPERIENCE

• Strong understanding of CPU and SoC architecture, including power delivery, PPA optimization, performance states, low-power modes, thermal management, and platform-level constraints.
• Experience with power integrity (PI), power delivery network (PDN) design, and system-level power management concepts, including IR drop, voltage droop, impedance optimization, decoupling strategies, and noise budgeting.
• Knowledge of silicon reliability, thermal management methodologies, and the interactions between silicon, package, and platform design required to achieve robust product operation.
• Proven ability to lead complex cross-functional technical initiatives across architecture, design, firmware, validation, package, and platform engineering organizations.
• Experience collaborating with power and performance modeling teams to drive target setting, architectural tradeoffs, and product optimization, along with ownership of technical workstreams through key product development milestones.

ACADEMIC CREDENTIALS

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline.

LOCATION:

Santa Clara, CA

This role is not eligible for visa sponsorship.

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Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD's “Responsible AI Policy” is available here.

This posting is for an existing vacancy.