IP Design engineer Job Listing at AMD in San Jose, CA (Job ID 85004-en-us)

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING 

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.  Together, we advance your career.  

THE ROLE:  

The focus of this role is to plan, build, and execute the design of new and existing features supporting AMD's FPGA IP and device development, resulting in efficient, error-free and timely Silicon and Solution delivery.  

THE PERSON:  

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.  

KEY RESPONSIBILITIES:  

• Collaborate with architects, hardware engineers, and firmware engineers to understand the product requirements and IP features 
• Build early-stage RTL designs based on product and architecture intent driving Silicon and Solution co-development 
• Build design infrastructure tool flow using AI to accelerate IP integration, delivery timelines for cross-functional development 
• Drive engineering alignment on current and/or next-gen products across technology nodes using data-driven methodology for internal HW-SW development 
• Support functional simulation activities and SW quality checks 
• Collaborate with various engineering groups across different geographical locations

PREFERRED EXPERIENCE:  

• Strong understanding of different design stages from RTL to GDS implementation 
• Proficient in RTL design implementation of Digital/Analog blocks using Verilog/System Verilog. 
• Knowledge in VLSI design, Design Automation, and IC design. 
• Knowledge of Physical Design (floor planning, synthesis, place & route) and Static Timing Analysis. 
• Basic knowledge of EDA Tools (like Synopsys DC Compiler, Primetime, VCS, Cadence Virtuoso). 
• Experience with UVM/OVM and/or Verilog, System Verilog test benches, BFMs and usage of simulation tools/debug environments is preferred. 
• Basic understanding of FPGA architecture and customer usage model is a plus. 
• Proficiency in Perl, Tcl, Shell, Python and/or other scripting language. 
• Excellent written and verbal communication skills in English. 
• Self-motivated team worker with ability to work in a fast-paced work environment. 

ACADEMIC CREDENTIALS:  

• Bachelors or Masters degree in computer engineering/Electrical Engineering  

This role is not eligible for visa sponsorship. 

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Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD's “Responsible AI Policy” is available here.

This posting is for an existing vacancy.