Description
WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
THE ROLE:
We are seeking an experienced High-Speed Ethernet / PHY Bring‑Up Engineer to lead the development, bring-up, and validation of high‑speed network interfaces across copper and optical media. The ideal candidate will have deep expertise in Ethernet physical layer technologies, signal integrity debugging, SerDes tuning, and interoperability testing with major networking vendors.
THE PERSON:
We are seeking an Engineer who has expertise in bring up high-speed Ethernet links and debug signal integrity issues - Perform physical layer (PHY) bringup for network ports, including fiber optics and copper connections - Debug MAC/PHY configuration, auto-negotiation, and link training issues (ANLT) - Validate and tune link performance across various optical transceivers (SFP+, QSFP-DD, OSFP) and ensure seamless interoperability with third-party switch vendors like Cisco, Arista, and Juniper - Develop tools for PRBS, eye-dump, BER to troubleshoot physical layer issues and do SerDes tuning - familiarity with I2C.
KEY RESPONSIBILITIES:
High-Speed Link Bring-Up & Validation
- Bring up high‑speed Ethernet links 100G/200G/400G/800G+) and debug signal integrity (SI) issues across copper and optical channels.
- Perform physical-layer (PHY) bring‑up for a wide range of network ports, including SFP+, QSFP-DD, OSFP, DACs, and active optical cables.
- Debug and optimize MAC/PHY configurations, including auto‑negotiation, link training (AN/LT or ANLT), and SerDes initialization sequences.
- Validate link performance under various channel conditions using optical transceivers from multiple vendors.
- Ensure seamless interoperability with third‑party switch and router vendors (e.g., Cisco, Arista, Juniper).
Signal Integrity & SerDes Debug
- Identify and resolve SI issues such as reflections, crosstalk, insertion loss, return loss, and equalization misconfigurations.
- Perform SerDes tuning (CTLE, DFE, TX FIR tap adjustments) to achieve stable and optimal link margins.
- Analyze eye diagrams, bathtub curves, and receiver margins to evaluate link health.
Test & Diagnostic Tool Development
- Develop or enhance internal tools for:
- PRBS generation and checking
- Eye-dump collection and analysis
- Bit Error Rate (BER) measurements
- Live signal monitoring for PHY and SerDes
- Automate diagnostics and link health reporting to accelerate root cause isolation.
Hardware Interface Debug
- Debug low‑speed interfaces such as I²C/I3C used for module communication, EEPROM access, DDM/DOM data, and transceiver control.
- Work closely with hardware teams to validate schematics, layout constraints, and ensure compliance with high‑speed design guidelines.
Cross‑Functional Collaboration
- Partner with electrical engineers, board design teams, ASIC/SerDes teams, firmware developers, and signal integrity engineers to ensure robust PHY integration.
- Support manufacturing and validation teams with test plans, bring-up scripts, and troubleshooting guidelines.
REQUIRED QUALIFICATIONS:
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
- Extensive experience working with high‑speed Ethernet PHYs or SerDes bring‑up.
- Strong understanding of Ethernet standards (IEEE 802.3), PAM4/NRZ signaling, and link training mechanisms.
- Hands-on experience with oscilloscopes, VNAs, BERTs, logic analyzers, and high‑speed probing.
- Demonstrated ability to debug signal integrity issues and tune SerDes parameters.
- Experience with optical transceivers and vendor ecosystems (SFP+, QSFP28, QSFP‑DD, OSFP, etc.).
- Proficiency with low-speed bus protocols such as I²C, MDIO, SPI.
- Strong scripting skills (Python preferred) for automation and diagnostics.
PREFERRED QUALIFICATIONS:
- Experience with interoperability testing against major switch vendors (Cisco, Arista, Juniper, Broadcom, etc.).
- Familiarity with board-level design, impedance control, and layout review.
- Experience with PRBS testing, BER analysis, and eye diagram evaluation tools.
- Knowledge of firmware or embedded development for PHY configuration.
- Background working with Broadcom, Marvell, Credo, Inphi, or similar PHY/SerDes IP.
ACADEMIC CREDENTIALS:
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
#LI-BW1
This role is not eligible for visa sponsorship.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
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