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Company: AMD
Location: San Jose, CA
Career Level: Mid-Senior Level
Industries: Technology, Software, IT, Electronics

Description



WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_



THE ROLE: 

As a senior design engineer in our FPD BRICS team, you will be responsible for leading and optimizing the Fabric PPC in the Adaptive & Embedded Computing Group (AECG). You will be driving new ideas and capabilities in the programmable fabric in current and future products. You will be leading the evaluation of future architectures by closing working with Architecture and Manufacturing teams. You will enable test chip designs and provide technical direction for skilled design engineers to help evaluate and realize key IP and technologies. You will be reviewing IP designs for quality, performance, power, and cost.  Additionally, you will interact with the various Silicon development teams including  digital and analog circuit designers, custom layout designers, physical designers, integration teams, and sign-off teams.


THE PERSON:

A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.

KEY RESPONSIBLITIES:

  • Execute BRICS team supporting Fabric research and development
  • Enable new capabilities in the FPGA fabric to improve PPC
  • Evaluate key new features in the fabric with deep understanding of software capabilities
  • Design Reviews to reduce product risk, improve PPC and schedule
  • Evaluate and develop yield improvement techniques
  • Understand product roadmaps and enable new foundry technologies
  • Leverage and deploy AMD solutions in the fabric


PREFERRED EXPERIENCE:

  • Programmable logic fundamentals
  • Next generation process and packaging technologies
  • Binning and circuit margins, including VID, Aging
  • Regulators, SRAM design, LUTs, NOCs, Clocking
  • Circuit techniques for high performance and low power operations
  • Industrial and automotive FUSA requirements
  • Design for Manufacturing and Design for Debug
  • Micro-architecture of dense, repeating structures
  • Strong written and verbal communication skills

 

ACADEMIC CREDENTIALS:

  • Bachelors or Masters degree in computer engineering/Electrical Engineering 

 

LOCATION: San Jose, CA 

 

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Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.


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