DFX Integration and Scan/ATPG Engineer Job Listing at AMD in Markham, ON (Job ID 62164-en-us)

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

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THE ROLE: 

As a DFX Integration and Scan/ATPG Engineer specializing in System-on-Chip (SoC) designs, your role encompasses the development and validation of advanced Design for Test (DFT) methodologies, including Streaming Scan Network (SSN) and Internal JTAG (IJTAG) implementations. You will architect RTL-centric DFT flows, integrate high-bandwidth IJTAG over SSN networks, and collaborate closely with cross-functional teams to ensure seamless integration and verification of DFT features across SoC, IP, and product domains. Your expertise will drive the insertion and validation of DFT logic, utilizing industry-standard simulation tools, and contribute to silicon characterization and validation efforts.

THE PERSON: 

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. 

KEY RESPONSIBILITIES: 

• Developing test infrastructure, including SSN(Scan Streaming Network) daisy chain planning, SSN Insertion/Verification.

• Verification of IJTAG Testbenches.
• Insertion/Verification on In-System Test Controller (ISTC).
• Insertion of High bandwidth IJTAG over SSN Network.
• SoC level IJTAG verification and SSN Continuity Verification.
• Writing procedures in PDL format to help with creation of SoC level Scan initialization sequence/preamble.
• Providing support to Scan/ATPG team and help with ICLNetwork/SSN simulations.

PREFERRED EXPERIENCE: 

• Familiar with entire ASIC design flow, hands-on working experience on ASIC DFT design and verification is an advantage.
• Excellent knowledge of Digital Electronics, RTL/verilog, computer architecture.
• Familiarity with IEEE standards like 1149, 1500, and 1687.
• In-depth knowledge of DFT EDA tools (Siemens/Synopsys).
• Some scripting languages like Tcl/Perl/Csh or Python is required to help with automation tasks.

ACADEMIC CREDENTIALS: 

• Bachelor or Masters degree in Computer Engineering, Electrical Engineering, or relevant fields.

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Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.