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The Product Verification team is looking for a Senior DFT Engineer to join exciting career on Scan, MBIST and iJTAG test development of latest 7nm Versal MPSoC (Multi Processor System on Chip) products and beyond. The candidate will work on complex SoC designs having ARM based Processor to critical IPs which provide automotive, data centre, machine learning and high-speed communication solutions.
Key responsibilities include but are not limited to:
- Develop Structural Test Patterns (Scan/MBIST/iJTAG) for multiple IPs in Next Generation Xilinx MPSoCs
- Achieve Structural test coverage target of the Digital logic, SRAMs and Mixed-Signal IPs using ATPG and different fault models
- Develop iJTAG Network and Memory BIST / Repair patterns
- Design FPGA Logic using Xilinx vivado software to apply test patterns and enhance the diagnostic capability
- Pre-silicon verification of DFT schemes and patterns using Industry standard tools.
- Diagnose and debug the pattern failures on ATE to root cause the problem
- Responsible for implementing techniques to Optimize Test Time, Dynamic IR drop in scan shift and Yield improvement
- Work closely with Design Team and Product Engineering Teams to quickly resolve issues and meet high volume production schedule
- Bachelor or Master's degree in Electrical/Electronic/Computer Engineering
- 2-5 years' experience in DFT and ATPG
- Knowledge of Fault modelling, Scan architecture, Scan compression and Memory testing techniques
- Expertise with Industry standard tools like TestKompress, DFT advisor, DFT Compiler, VCS
- Experience in Gate Level Simulation and Debug
- Good understanding of Digital Design and ASIC design flow
- Knowledge in VHDL/Verilog and IEEE 1149.1 standard
- Knowledge of Perl / Shell Scripting and C++ is a plus
- Knowledge of FPGA and Vivado Software is a plus
- Self-motivated and a strong team-player
- Strong analytical and problem-solving skills
- Ability to learn new tools and technologies
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