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This is a post-silicon validation engineer position in the Wired and Wireless Group to perform but not limited to key activities as silicon bring up, functional verification and performance optimization, silicon issue debug and protocol compliance tests with a focus on high speed IO SerDes.
- Education : Bachelors/Masters degree in Electrical/Electronics/Computer Engineering
- Experience in high speed IO SerDes (PHY/PCS) design/validation, pre-/post-silicon verification.
- Extensive knowledge of the physical and protocol levels of latest industry standards such as PCIe, Display Port, JESD, SDI, OIF-CEI-11G/25G/56G/112G-VSR/SR/MR/LR, IEEE 802.3 KR/CR/CAUI/GAUI etc.
- Strong programming/scripting skills (eg. Python, C/C++, Perl, TCL et.) for firmware development, test methodology development and test automation
- Hands on experience and strong knowledge with FPGA/ASIC based SerDes debug techniques and methodologies
- Extensive experience with common lab equipment, including BERT, analyzers, oscilloscopes, PNA/VNA etc
- In-depth knowledge of SerDes general architectures and link level system analysis is an asset
- Experience in system level serial link analysis and simulation, system performance optimization and standard/architecture level study using tools such as Python, Matlab, ADS etc. is an added advantage.
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