Date: Oct 12, 2020
Our Exciting Opportunity
Would you like the chance to do your thesis together with one of the world's leading technology companies? We are on a quest to enable communication for everyone and everything and we believe that we do that by being as innovative as possible. If you want to help us to be even more innovative – then you are on the right track! We want you to become a part of a truly global company working across borders in 180 countries, offering a diverse, performance-driven culture & an innovative & engaging environment where employees enhance their potential every day. Come and learn and grow with us at Ericsson!
Our department ASIC/FPGA Design in Kista are responsible for Digital ASIC/FPGA development for all existing and future mobile standards including 5G. This is done in close cooperation with internal and external stake holders such as standardization teams and market leading vendors. We are working with state-of-the-art technologies, tools and methodologies from our vendors.
Power consumption has become a leading concern for SoC aimed at 5G products that demand increased functionality, smaller form factors, and low energy footprint. For most EMCA IP blocks a hierarchical clock gating mechanism ensures power savings based on actual processing need but for some blocks this approach cannot be employed. This implies that these blocks have to rely on a high local clock gating efficiency to meet the set power requirements. For this purpose, designers have to manually analyze and optimize the blocks to improve the combinational and sequential clock gating. But this flow is error-prone and time-consuming as it requires running long simulations to ensure the RTL changes have not introduced functional errors. The scope of this Thesis is to evaluate and deploy a novel flow that features automatic power optimization along with integrated formal verification guarantees for bug-free RTL. The flow will be applied on a set of EMCA IP blocks to reduce design efforts and produce energy efficient IPs even when time to market is the highest priority for a project.
The assignment of this Thesis is twofold. The first goal is to employ and integrate the automated power optimization flow into the existing RTL design process and connect the verification environment to the low-level power analysis tools.
- Realization of a flow that comprises in-house and commercial frontend power tools.
- Identifying the optimal time windows and testcases for power optimization for the candidate IP blocks.
The second goal is to analyze and optimize the set of IP blocks, using the automated flow.
- Demonstrate how this flow can bring together analysis, optimization, and formally-verified automatic RTL generation to boost the clock gating efficiency at the late stages of the IP process.
- Quantify the achievable power savings and area/timing tradeoffs. Assess the impact on power of potential design transformations and suggest further improvements in the RTL code.
To be successful in the role you must have
- • MsC in electrical/computer engineering, computer science or similar.
- • Knowledge in ASIC design and Tcl scripting for EDA tools is preferred.
”Performance comparison between APB and AHB access to IQC Device Processor packet TX and RX memories including transmitting packets between those using the IQ Control, IQC, packet switch.
The thesis consists of two parts, a design part and a performance investigation part, which are dependent on each other.”
- Exchange the present APB/MIRI interface to IQC packet RX and TX memories to AHB interface.
- This would include prestudy of how the AHB shall connect to the IQC DP packet memories. And how to implement the AHB.
- Develop performance tests for IQC packet transmission from one processor to another using the IQC DP packet memories.
- These performance test would include latency and throughput for different size packets.
- A comparison would then be made between the present APB/MIRI solution and the new AHB connection.
- This also would include a prestudy of how to implement and visualize the performance in a graphical quick and easy to understand way using the existing SystemVerilog UVM verification environment.
- To analyze how the performance scales with more number of device processors, DP, functions with same AHB interface connecting multiple DP RX ports (if it gets better or worsens or no change)
- This will help identify if single AHB port is enough or we need to add extra AHB port when we have more DP functions or more DPs.
- Packet loss and packet bit errors should be measured.
Implementation size and timing:
- Comparizon between the APB MIRI and the AHB interface design.
This project aims at students in MSc. Background in wireless communication is preferred.
“Comparison of Serial Protocols: Industry Standard PCIE versus Ericsson proprietary SXP, and which direction should Ericsson choose for future ASICs”
PCIE is an industry standard serial protocol.
SXP is a proprietary serial protocol developed by Ericsson.
Comparison of Performance: PCIE versus SXP:
The expected performance can be calculated theoretically, and measured in practice using simulation.
Performace should consider: Single transfers, Block transfer and DMA support.
Performance should consider: latency and bandwidth.
A comparison between the Protocols should also consider all other aspects:
Cost: Chip area, License Fee, Implementation cost (eg man hours of effort for design / integration / verification)
Power: Low power or power saving modes
Reliability/Robustness: What is the maximum bit error rate(BER) that the protocol will tolerate.
Ease of use: How easy is it for SW to use?
Interesting Features: Eg. Cascading
Compatibility: Interoperability with other Ericsson ASICs, interoperability with standard components (eg FPGAs with built in PCIE)
Portability: How easy is it to migrate between technologies.
A practical aspect of this thesis work will be to develop performance measurement tests for existing designs using simulation. It might also be possible to use real hardware in the lab.
This master thesis should provide an opportunity for a deep dive into understanding the PCIE protocol.
The conclusion should be a comparison between the use of PCIE or SXP and a recommendation on how serial interfaces should be developed in the future at Ericsson.
What´s in it for you?
Here at Ericsson, our culture is built on over a century of courageous decisions. With us, you will no longer be dreaming of what the future holds – you will be redefining it. You won't develop for the status quo, but will build what replaces it. Joining us is a way to move your career in any direction you want; with hundreds of career opportunities in locations all over the world, in a place where co-creation and collaboration are embedded into the walls. You will find yourself in a speak-up environment where empathy and humanness serve as cornerstones for how we work, and where work-life balance is a priority. Welcome to an inclusive, global company where your opportunity to make an impact is endless.
What happens once you apply?
To prepare yourself for next steps, please explore here: https://www.ericsson.com/en/careers/job-opportunities/hiring-process
If you have any specific questions about this role, please contact recruiter Sylwia Kwiecien at firstname.lastname@example.org.
Hiring Manager: Line Manager in ASIC & IP Design Unit
Kindly note that we cannot process applications sent via email.
Location for this role: Stockholm, Sweden
Last day to apply: 26.10.2020
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Do you believe that an organization fostering an environment of cooperation and collaboration to execute with speed creates better business value? Do you value a culture of humanness, where fact based decisions are important and our people are encouraged to speak up? Do you believe that diverse, inclusive teams drive performance and innovation? At Ericsson, we do.
We provide equal employment opportunities without regard to race, color, gender, sexual orientation, transgender status, gender identity and/or expression, marital status, pregnancy, parental status, religion, political opinion, nationality, ethnic background, social origin, social status, indigenous status, disability, age, union membership or employee representation and any other characteristic protected by local law or Ericsson's Code of Business Ethics.
Primary country and city: Sweden (SE) || || Stockholm || Stud&YP
Req ID: 431482
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